Use of ASICs (application specific integrated circuits) has become widespread in the semiconductor industry as giving circuit design engineers a relatively high amount of functionality in a relatively small package. In particular, ASICs are customizable integrated circuits that are customized to implement a circuit specified by a design engineer (a “custom circuit design”). The term “ASIC” actually refers to a variety of integrated circuit (IC) styles that vary in degree of customizability, including standard cells, gate arrays, and FPGAs. As a general rule, the more customization that is required, the more expensive the ASIC will be and the longer the ASIC will take to fabricate.
In forming ASICs generally, several layers will be required. FIG. 1 shows a partial cross-sectional view of a generic integrated circuit. First, active layers 110 are formed on a semiconductor substrate. The active layers 110 include devices such as transistors and diodes. Many active layer devices are formed independently of one another, i.e., they are not connected to form a circuit. Thus, once active layers 110 are formed, conducting layers, which are often composed of a metal such as aluminum or copper, are formed over the active layers to interconnect the devices, thereby forming a circuit. Several conducting layers may be required to completely interconnect the devices to form a useful circuit. Four conducting layers, M1 120, M2 130, M3 140, and M4 150, are shown in FIG. 1. Of course, different types of ICs or ICs fabricated using different processes may require more or less than four metal layers for circuit interconnection.
In between each conducting layer is an insulating layer 115, 125, 135, 145 as shown in FIG. 1. Insulating layers are present to prevent shorts between conducting layers. To interconnect the conducting layers, vias 116 are formed through the insulating layers and are filled with conducting material (e.g., metal).
In forming the structure of FIG. 1, after the active layers 110 are formed, an insulating layer 115 is formed over the active layers 110, for instance, by growth or deposition of insulating material. Next, a masking step is utilized to form vias in the insulating layer, as is generally known in the art. Such masking often entails depositing a photoresist layer and patterning the layer using ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching the insulating layer in accordance with the photoresist pattern. After forming the vias, a conducting layer is deposited and then patterned using a similar masking process, so that metal (or other conductor) remains only in desired locations. The process is repeated for each insulating layer and conducting layer required to be formed.
Thus each conducting layer required to be formed generally demands at least two masking steps: one step to form vias through the insulating layer to connect to the layer below and one step to form connection wires or lines. Unfortunately, each mask step required generally entails significant time and expense.
At the active layer level, ASIC active devices are generally arranged to form function blocks, also commonly referred to as “cells” or “modules.” To interconnect the devices, “horizontal” and “vertical” connection lines are formed in the conducting layers. As is well understood in the art, any two points can be connected using horizontal and vertical connection lines (that is, connection lines that are orthogonal with respect to one another). While such interconnections can be done in one metal layer, more typically, horizontal connections are formed in a first metal layer and vertical connections are formed in a second metal layer with an insulating layer having vias formed between to connect the two layers.
Of great importance to an IC designer in implementing circuit designs with an ASIC is the functionality available from the ASIC. That is, the IC designer may have circuit designs which include a large number of different combinational functions (e.g., Boolean logic), sequential functions (e.g., flip-flops, latches), and/or memory functions (e.g., SRAM), and the designer would prefer an ASIC that efficiently implements a significant majority of his or her design so that the overall design is implemented in the smallest space possible. Since ASICs are generally formed of function blocks, the functionality available in each of these devices will be primarily determined by the architecture within each function block.
Also important to an IC designer is customization time. Particularly during the design stages, the IC designer wants to obtain a model, or prototype, of his or her designs quickly so that the designs can be tested and used with other circuitry.
One approach to ASICs is the gate array. In gate arrays, function blocks 210 are generally arranged to form a regular array 200, shown in FIG. 2. Such function blocks are generically designed and include a particular number, size, arrangement, and type of semiconductor devices, e.g., transistors. An example gate array function block 210 is shown in FIG. 3, having six transistors of varying size and drive capability. Such an array, prior to implementing a custom circuit design, is sometimes referred to as a “base array.” Prior to array customization, the base array transistors are primarily freestanding, having few, if any, internal connections to one another. Accordingly, the base array of such a gate array is sometimes referred to as a “sea of gates.”
To customize the sea-of-gates gate array to implement a particular custom circuit design, various connections are made among the active devices within the function block (local interconnections) and connections are made among function blocks (global interconnections). In other words, routing is customized. There are generally at least three to five layers of connecting wires formed over the active device layer, and each layer requires at least two masking steps to form (one step to form vias to the layer below and one step to form connecting wires). Thus, at least six to ten masking steps must be undertaken to fully customize a sea-of-gates type gate array. So although the sea-of-gates gate array allows for circuit flexibility by allowing for implementation of combinational and sequential functions, as well as memory functions, such a gate array will bear the costs of multiple masking steps for routing. In addition, because of the multiple masking steps required, production time for customizing the gate array can be considerable. Still, because the base array is generic, capable of implementing a wide variety of custom circuit designs, wafers can be prefabricated through the base array and stockpiled until a custom circuit design is received, thereby minimizing the mask steps required for customization and speeding production of a customized circuit.
A second approach to gate arrays, and one having a more rapid customization time, is the field programmable gate array (FPGA). The FPGA is prefabricated through all layers (active layers, metal layers, and insulating layers). FPGAs are also arranged into a regular array of function blocks as shown in FIG. 2. The FPGA function blocks are often composed of a fixed logic circuit of multiplexers and other logic gates. A sample FPGA function block 210′ is illustrated in FIG. 4. Each function block 210′ can perform a wide variety of logical functions. The function to be performed by the fixed logic circuit is selected by determining the input signals to the function block. Thus, to customize an FPGA, an IC designer can specify signals (including power and ground) to be coupled to the inputs and outputs for each function block thereby determining the logical function the function block is to perform.
FPGA customization time tends to be more rapid than other types of gate arrays because the active device layer and all insulating and conducting layers are fixed. In other words, both the local interconnect structure and the global interconnect structure are fixed. The global interconnect structure is formed of a plurality of intersecting wires. At each intersection is either a fuse or a programmable RAM bit. Thus, to program function-block functionality (i.e., to control input signals to each function block), either a fuse is stressed to melt and form a connection at the intersection, or a RAM bit is programmed to form this connection. Since the entire FPGA structure is fixed by the manufacturer, no additional mask steps are required and FPGA programming can actually be done by the IC designer with equipment and software at his or her own place of business. Commonly, an IC designer will specify a logical function (often from a library) that the designer wishes the function block to perform and the signals to be coupled to function block inputs and outputs are then determined and programmed by software.
Despite rapid and easy customization, FPGAs currently available have drawbacks. FPGAs are often used in intermediate design steps for test purposes, but cannot often be used in a final product: because of the nature of the FPGA interconnect structure, an FPGA often will not meet the performance expectations of the final product (e.g., timing) and thus has only limited use in test situations.
At the other end of the spectrum from FPGAs are standard cell-type ASICs. A standard cell 300 is generally illustrated in FIG. 5. As shown, a typical standard cell includes several horizontal rows 302 of function blocks 304, sometimes referred to as “cells,” where the function blocks have the same height, but unequal width. Although each cell has a pre-defined number of devices, the cells are individualized for use in a particular custom circuit design by optimizing device size and placement as well as eliminating extraneous pre-defined devices. Therefore, the cells are not all identical and prefabrication (fabrication prior to receiving a custom circuit design) is not possible.
To simplify the design process, various vendors have developed standard cell libraries. Each library includes many components (sometimes also referred to as “books” or “macros”), each component defining a logical function that can be formed using one or more cells. An example library component 402 is shown in FIG. 6 as a D-type flip-flop 404 and buffer 406. Literally thousands of pre-designed components are available in libraries for selection by the IC designer. Use of the standard cell libraries is advantageous in that designers save time, money, and reduce risk by using pre-designed and pretested logic. Unlike gate arrays which have fixed device size, each cell can further be optimized individually in that every transistor can be chosen, for example, to maximize speed, minimize area, or provide proper drive strength. Further, unlike gate arrays, the spacing (the channels) between rows in a standard-cell type ASIC can be adjusted. The designer then defines the placement of the cells and the interconnect routing. Therefore, standard cells provide similar performance and flexibility advantages of a full-custom ASIC but at reduced design time and risk.
Although the use of libraries aids in the automation of the process of assembling the ASIC, all of the masks used to form a standard-cell type ASIC are customized since no part of the circuit structure is completely known prior to receiving a custom circuit design. Accordingly, standard cells require fabrication of all layers including active layers, conducting layers, and insulating layers. So while standard-cell type ASICs offer considerable design flexibility, they are expensive and require considerable time to fabricate. Therefore, they tend to be used after initial designs are completed and tested with FPGAs or other partially pre-fabricated gate arrays, such as sea-of-gates-type gate arrays.
As IC designers create more and more complex IC designs, they are demanding more functional capabilities from ASICs while further demanding that customization time remain low, that ASIC die size remain small, and that reliability remain high. So, although available ASICs allow some flexibility to the IC designer, improved architectures are always desirable. Particularly desirable is any architectural design that allows increased flexibility and functionality while reducing customization time.